mingxin@zhao:~/about
Mingxin Zhao

Mingxin Zhao

Staff Engineer · Alibaba Group

Shanghai, China — RISC-V toolchains

risc-v dynamic binary translation jit compilers cpu simulation quantization

About

I'm a Staff Engineer at Alibaba Group, focused on dynamic binary translation, JIT engines, and performance optimization. I previously worked there as a Senior Software Engineer on QEMU, LLVM-based CPU compiler optimization, and the design of dynamic binary translators for the RISC-V architecture. Before moving into industry, I earned my Ph.D. from the Institute of Semiconductors, Chinese Academy of Sciences (ISCAS), where my research spanned machine vision on edge-computing chips, neural network compression, and hardware–software co-design.

Experience

Alibaba Group 2026.04 – present
Staff Engineer
  • Develop and maintain the dynamic binary translator.
  • Build and extend the JIT engine.
  • Optimize runtime performance across the translation pipeline.
Alibaba Group 2022.07 – 2026.04
Senior Software Engineer
  • Developed and maintained QEMU for RISC-V targets.
  • Optimized the CPU compiler within the LLVM framework.
  • Designed and developed a dynamic binary translator.
Huawei — 2012 Lab 2021.05 – 2022.06
Technology Research Engineer · intern
  • Developed auto-tensorization compiler techniques, mapping fine-grained user code to tensor-level hardware primitives through polyhedral modeling.
  • Processed data from dynamic vision sensors (DVS), whose ultra-high dynamic range and temporal resolution — together with a motion-only response — make them well-suited to automotive applications when paired with dedicated optimizations.
SenseTime Research 2020.07 – 2020.10
Researcher · intern
  • Built a flexible deep-learning quantization framework that bridges a range of quantization algorithms to diverse hardware backends.

Education

Institute of Semiconductors, CAS 2017.09 – 2022.06
Ph.D.
  • Advised by Prof. Nanjian Wu, whose team develops vision chips for ultra-low-power, near-sensor vision processing.
  • Deployed convolutional neural networks on a SIMD-style vision chip using low-bitwidth quantization and structured pruning.
  • A 256-PE SIMD array controlled by a RISC scalar MPU: during convolution, adjacent pixels map onto neighboring processing elements with dedicated accumulation paths, so image data is consumed spatially with no im2col layout reorder.
University of Science and Technology of China 2013.09 – 2017.07
Bachelor · Applied Physics
  • Developed strong foundations in analytical reasoning and mathematical modeling.